View FDW2520C_6858194.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. adn8830 thermoelectric cooler controller features high efficiency small size: 5 mm 5 mm lfcsp low noise: <0.5% tec current ripple long-term temperature stability: 0.01 c temperature lock indication temperature monitoring output oscillator synchronization with an external signal clock phase adjustment for multiple controllers programmable switching frequency up to 1 mhz thermistor failure alarm maximum tec voltage programmability applications thermoelectric cooler (tec) temperature control resistive heating element control temperature stabilization substrate (tss) control functional block diagram pid compensation network temperature measurement amplifier pwm controller from thermistor temperature set input vo ltag e reference v ref oscillator frequency/phase control p-channel (upper mosfet) n-channel mosfet drivers p-channel (lower mosfet) n-channel general description the adn8830 is a monolithic controller that drives a thermo- electric cooler (tec) to stabilize the temperature of a laser diode or a passive component used in telecommunications equipment. this device relies on a negative temperature coefficient (ntc) thermistor to sense the temperature of the object attached to the tec. the target temperature is set with an analog input voltage either from a dac or an external resistor divider. the loop is stabilized by a pid compensation amplifier with high stability and low noise. the compensation network can be adjusted by the user to optimize temperature settling time. the component values for this network can be calculated based on the thermal transfer function of the laser diode or obtained from the lookup table given in the application notes section. voltage outputs are provided to monitor both the temperature of the object and the voltage across the tec. a voltage reference of 2.5 v is also provided.
rev. c e2e adn8830especifications (@ v dd = 3.3 v to 5.0 v, v gnd = 0 v, t a = 25 c, t set = 25 c, using typical application configuration as shown in figure 1, unless otherwise noted.) parameter symbol conditions min typ max unit temperature stability long-term stability using 10 k ? C = ( ) = ? = ? = ? = = C + C + = = < < C + ? < = ( = ? = ) C )
rev. c adn8830 e3e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adn8830 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v input voltage . . . . . . . . . . . . . . . . . . . . . . . gnd to v s + 0.3 v storage temperature range . . . . . . . . . . . . . C + C + ( ) ( ) sd dd s s s dd d s s ss s d s C + () C + () C + ()
rev. c e4e adn8830 pin function descriptions pin no. mnemonic type description 1 thermfault digital output indicates an open or short-circuit condition from thermistor. 2 thermin analog input thermistor feedback input. 3 sd d ds s d + C
rev. c t ypical performance characteristicseadn8830 e5e time (20ns/div) 0 00 0 vo lta ge (1v/div) 00000000 p1 n1 v dd = 5v t a = 25 c tpc 1. n1 and p1 rise time time (20ns/div) 0 00 0 vo lta ge (1v/div) 00000000 v dd = 5v t a = 25 c p1 n1 tpc 2. n1 and p1 fall time 360 320 0 phase shift (degrees) 160 120 80 40 240 200 280 vphase (v) 2.4 0.4 0.8 1.2 1.6 2.0 0 sync in = 1mhz t a = 25 c tpc 3. clock phase shift vs. phase voltage 320 0 phase shift (degrees) 160 120 80 40 240 200 280 vphase (v) 2.4 0.4 0.8 1.2 1.6 2.0 0 sync in = 200khz t a = 25 c 360 tpc 4. clock phase shift vs. phase voltage temperature ( c) 2.480 2.475 2.455 e40 85 e15 v ref ( v) 10 35 60 2.470 2.465 2.460 tpc 5. v ref vs. temperature r freq (k ) 1,000 800 0 01, 500 250 500 750 1,000 1,250 600 400 200 v dd = 5v t a = 25 c switching frequency (khz) tpc 6. switching frequency vs. r freq
rev. c e6e adn8830 temperature ( c) 1,000 920 e40 85 e15 switching frequency (khz) 10 35 60 980 960 940 930 990 970 950 v dd = 5v r freq = 150k tpc 7. switching frequency vs. temperature temperature ( c) 70 30 e40 85 e15 offset voltage ( v) 10 35 60 55 45 35 65 60 50 40 tpc 8. offset voltage vs. temperature common-mode voltage (v) 200 e100 e400 02.0 0.2 offset voltage ( v) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 100 0 e200 e300 tpc 9. offset voltage vs. common-mode voltage switching frequency (khz) 200 1,000 300 400 500 600 700 800 900 45 40 0 supply current (ma) 20 15 10 5 30 25 35 v dd = 5v t a = 25 c using circuit shown in figure 1 tpc 10. supply current vs. switching frequency temperature ( c) 2.06 2.02 e40 85 e15 therm fault upper threshold (v) 10 35 60 2.04 2.03 2.05 t pc 11. open thermistor fault threshold vs. temperature temperature ( c) 0.26 0.23 e40 85 e15 therm fault lower threshold (v) 10 35 60 0.25 0.24 tpc 12. short thermistor fault threshold vs. temperature
rev. c adn8830 e7e application notes principle of operation the adn8830 is a controller for a tec and is used to set and stabilize the temperature of the tec. a voltage applied to the input of the adn8830 corresponds to a target temperature setpoint. the appropriate current is then applied to the tec to pump heat either to or away from the object whose tem- perature is being regulated. the temperature of the object is measured by a thermistor and is fed back to the adn8830 to correct the loop and settle the tec to the appro priate final temperature. for best stability, the thermistor should be mounted in close proximity to the object. in most laser diode modules, the tec and thermistor are already mounted in the unit and are used to regulate the temperature of the laser diode. a complete tec controller solution requires: ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ?
rev. c e8e adn8830 response of the tec tempctl can be expressed as tempctl tempset thermin = () + C tempset voltage, and the output of the input amplifier will be 1.5 v. the voltage at tempctl is then fed into the compensation amplifier whose frequency response is dictated by the compen- sation network. details on the compensation amplifier can be found in the compensation loop section. when configured as a simple integrator or pid loop, the dc forward gain of the compensation section is equal to the open-loop gain of the compensation amplifier, which is over 80 db or 10,000. the output from the compensation loop at compout is then fed to the linear amplifier. the output of the linear amplifier at out b is fed with compout into the pwm amplifier whose output is out a. these two outputs provide the voltage drive directly to the tec. including the external transistors, the gain of the differential output section is fixed at 4. details on the output amplifiers can be found in the output driver amplifiers section. 1.5v input amplifier a v = 20 compensation amplifier a v = z2/z1 1.5v z1 a v = 4 pwm/linear amplifiers out a out b z2 tempset thermin 4 2 12 13 14 19 9 tempctl compout compfb figure 2. signal flow block diagram of the adn8830 thermistor setup the temperature of the thermal object, such as a laser diode, is detected with a negative temperature coefficient (ntc) thermistor. the thermistor C C
rev. c adn8830 e9e although the thermistor has a nonlinear relationship to tem- perature, near optimal linearity over a specified temperature range can be achieved with the proper value of r x . first, the resistance of the thermistor must be known, where rrtt rtt rtt therm t low tmid t high == == == () t low and t high are the endpoints of the temperature range and t mid is the average. these resistances can be found in most thermistor data sheets. in some cases, only the coefficients corresponding to the steinhart-hart equation are given. the steinhart-hart equation is 1 11 3 t abnr cnr =+ () + () [] () t is the absolute temperature of the thermistor in kelvin (k = + ) r is the resistance of the thermistor at that temperature. based on the coefficients a , b , and c , r therm can be calculated for a given t , albeit somewhat tediously, by solving the cubic roots of this equation r therm =++ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ++ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CCC ? ? () x a t c = C = b c r x is then found as r rr r r rr rr r x tt t t tt tt t = + + C C r x should be 0.1% tolerance. naturally, the smaller the temperature range required for control, the more linear the voltage divider will be with respect to temperature. the voltage at thermin is v vref r rr x therm therm x = + () vref has a typical value of 2.47 v. the adn8830 control loop will adjust the temperature of the tec until v x equals the voltage at tempset (pin 4), which we define as v set . target temperature can be set by vmtt v set mid xmid = () + C t equals the target temperature, and m vv tt x high x low high low = C C v x for high, mid, and low are found by using equation 6 and substituting r t3 , r t2 , and r t1 , respectively, for r therm . the variable m is the change in v x with respect to temperature and is expressed in v/ ( ) ? ? ? ? ? ? ? ? m from equation 8 by the temperature range. thermin voltage range m t t max min = () C
rev. c e10e adn8830 to eliminate the resolution of the dac as the principal source of system error, the step size of each bit, v step , should be lower than the desired system resolution. a practical value for absolute dac resolution is the equivalent of 0.05 v step should be less than the value of m from equation 8 multiplied by the desired temperature resolution, or vcm step < () m is the slope of the voltage-to-temperature conversion line, as found from equation 8. from design example 2, where m = 25 mv/ number of bits vv fs step = () ( ) () C v fs is the full-scale output voltage from the dac, which should be equal to the reference voltage from the adn8830, vref = 2.47 v as given in the specifications table for the refer ence voltage. in this example, the minimum resolution is 11 bits. a 12-bit dac, such as the ad7390, can be readily found. it is important that the full-scale voltage input to the dac is tied to the adn8830 reference voltage, as shown in figure 4. this eliminates errors from slight variances of vref. thermistor fault and temperature lock indications both the thermfault (pin 1) and templock (pin 5) outputs are cmos compatible outputs that are active high. thermfault will be a logic low while the thermistor is operating normally and will go to a logic high if a short or open is detected at thermin (pin 2). the trip voltage for thermfault is when thermin falls below 0.2 v or exceeds 2.0 v. thermfault provides only an indication of a fault condition and does not activate any shutdown or protec- tion circuitry on the adn8830. to shut down the adn8830, a logic low voltage must be asserted on pin 3, as described in the shutdown mode section. templock will output a logic high when the voltage at thermin is within 2.5 mv of tempset. this voltage can be related to temperature by solving for m from equation 8. for most laser diode applications, 2.5 mv is equivalent to ( ) ( ) ( ) ? ? ? ? ? r freq , should be set to r f freq switch = () f switch is the switching frequency in hz. higher switching frequencies reduce the voltage ripple across the tec. however, high switch frequencies will create more power dissipation in the external transistors. this is due to the more frequent charging and discharging of the transistors ? ? ? ? ( ) phase shift v vref phase = () v phase is the voltage at pin 29, and vref has a typical value of 2.47 v. to ensure the oscillator operates correctly, v phase should remain higher than 100 mv and lower than 2.3 v. this is required for either internal clock or external sync hronization operation. a resistor di vider from vref to ground can establish this voltage easily, although any voltage source, such as a dac, could be used as well. if phase is not a consideration, for example with a single adn8830 being used, pin 29 can be tied to pin 6, which pro- vides a 1.5 v reference voltage.
rev. c adn8830 e11e the phase adjusted output from the adn8830 is available at syncout (pin 28). this pin can be used as a master clock signal for driving other adn8830 devices. multiple adn8830 devices can be either driven from a single master adn8830 device by connecting its syncout pin to each slave ss ss c = () c ss is the value of the capacitor in microfarads, and ss is the soft start time in milliseconds. to set a soft start time of 15 ms, c ss should equal 0.1
rev. c e12e adn8830 the unity-gain crossover frequency of the feedforward amplifier is given as f rc tec gain db 0 1 231 80 = () = ? = ? = ? = = ( ) ( ) ? ? (+) ? ?
rev. c adn8830 e13e using tempout to measure temperature the tempout pin is a voltage that is proportional to the difference between the target temperature and the measured thermistor temperature. the full equation for the voltage at tempout is tempout thermin tempset =+ () C tempout is 0 v to 3.0 v and is inde- pendent of power supply voltage. setting the maximum tec voltage and current the adn8830 can be programmed for a maximum output volt- age to protect the tec. a voltage from 0 v to 1.5 v applied to the vlim (pin 15) input to the adn8830 sets the maximum tec voltage, v tec, max . this voltage can be set with either a resistor divider or from a dac. because the output of the adn8830 is bidirectional, this voltage sets both the upper and lower limits of the tec voltage. the equation governing v tec, max is given in equation 17 and the graph of this equation is shown in figure 12. vv vlim tec max , . C = () () () () vtec v v out a out b = () + C v out a and v out b are the voltages at pins 19 and 9, respec- tively. the ripple voltage at pin 19 is filtered out internally and does not appear at vtec, leaving it as an accurate dc output of the tec voltage. the tec is driven with a differential voltage, allowing current to flow in either direction through the tec. this can provide heat transfer either to or from the object being regulated without the use of a negative voltage rail. the maximum output voltage across the tec is set by the voltage at vlim (pin 15). refer to the setting the maximum tec voltage and current section for details on this operation. with vlim set to ground, the maximum output voltage is the power supply voltage, v dd . to achieve a differential output, the adn8830 has two separate output stages. out a is a switched output or pulse-width modulated (pwm) amplifier, and out b is a high gain linear amplifier. although they achieve the same result, to provide constant voltage and high current, their operation is different. the exact equations for the two outputs are out a compout out b = () + C out b compout = () + CC compout is the voltage at pin 13. the voltage at compout is determined by the compensation network that is fed by the input amplifier, which receives its input voltage from tempset and thermin. equation 20 is valid only in the linear region of the linear amplifier. out b has a lower limit of 0 v and an upper limit of the power supply. because the compout voltage is not readily known, equa- tion 20 can be rewritten in terms of the tec voltage, vtec, which is defined as out b C out b vtec = + () ( )
rev. c ?4 adn8830 inductor selection in addition to the external transistors, the pwm amplifier requires an inductor and a capacitor at its output to filter the switched output waveform. proper inductor selection is important to achieve the best efficiency. the duty cycle of the pwm sets the out a output voltage and is d out a v dd = (22) the average current through the inductor is equal to the tec current. the ripple current through the inductor, i l , varies with the duty cycle and is equal to ? i vd d lf l dd clk = () 1? (23) where f clk is the clock frequency as set by the resistor r freq at pin 26 or an external clock frequency. refer to the setting the switching frequency section for more information. selecting a faster switching frequency or a larger value inductor will reduce the ripple current through the inductor. the waveform of the inductor current is shown in figure 13. time i tec inductor current (a) ? i l 1 f clk t = figure 13. current waveform through inductor it is important to select an inductor that can tolerate the maxi- mum possible current that could pass through it. most tecs are specified with a maximum voltage and current for proper and reliable operation. the maximum instantaneous inductor current can be found as ii i l max tec max l ,, . =+ 05 ? (24) where i l can be found from equation 23 with the appropriate duty cycle calculated from equation 22 with out a = v tec, max . design example 3 a tec is specified with a maximum current of 1.5 a and maxi- mum voltage of 2.5 v. the adn8830 will be operating from a 3.3 v supply voltage with a 200 khz clock and a 4.7 h induc tor. the duty cycle of the pwm amplifier at 2.5 v is calculated to be 75.8%. using equation 23, the inductor ripple current is found to be 664 ma. from equation 24, the maximum induc tor current will be 1.82 a and should be considered when selecting the inductor. notice that increasing the clock frequency to 1 mhz would reduce i l, max to 1.56 a. design example 4 using the same tec as above, the adn8830 will be powered from 5.0 v instead. here, the duty cycle is 50%, which happens to be the worst-case duty cycle for inductor current ripple. now dil equals 1.33 a with a 200 khz clock, and i l, max is 2.83 a. reducing the inductor ripple current is another compelling reason to operate the adn8830 from a 3.3 v supply instead. table ii lists some inductor manufacturers and part numbers along with some key specifications. the column i max refers to the maximum current at which the inductor is rated to remain linear. although higher currents can be pushed through the inductor, efficiency and ripple voltage will be dramatically degraded. this is by no means a complete list of manufacturers or ind uctors that can be used in the application. more information on these inductors is available at their websites. note the trade-offs between inductor height, maximum current, and series resistance. smaller inductors cannot handle as muh current and therefore require higher clock speeds to reduce their ripple current. they also have higher series resistance, which can lower the overall efficiency of the adn8830. pwm output filter requirements the switching of q1 and q2 creates a pulse width modulated (pwm) square wave from 0 v to v dd . this square wave must be filtered sufficiently to create a steady voltage that will drive the tec. the ripple voltage across the tec is a function of the inductor ripple current, the l-c filter cutoff frequency, and the equivalent series resistance (esr) of the filter capacitor. the equivalent circuit for the pwm side is given in figure 14. table ii. partial list of inductors and key specifications inductance ( h) i max (a) r s, typ (m )h eight (mm) part number manufacturer website 4.7 1.1 200 1 lpo1704-472m coilcraft www.coilcraft.com 4.7 1.59 55 2 a918cy-4r7m toko www.toko.com 4.7 3.9 48 2.8 up2.8b-4r7 cooper www.cooperet.com 4.7 1.5 90 3 do1608c-472 coilcraft www.coilcraft.com 4.7 1.32 56 3 cdrh4d28 4r7 sumida www.sumida.com 4.7 7.5 12 4.5 892nas-4r7m toko www.toko.com 4.7 * 5.4 18 5.2 do3316p-472 coilcraft www.coilcraft.com 10 2.7 80 2.8 up2.8b-100 cooper www.cooperet.com 15 8 32 8 do5022p-153hc coilcraft www.coilcraft.com 47 4.5 86 7.1 do5022p-473 coilcraft www.coilcraft.com * recommend inductor in typical application circuit figure 1.
rev. c adn8830 e15e out b c1 r1 r l l1 r2 pvdd p1 q1 n1 q2 out a v x denotes pgnd figure 14. equivalent circuit for pwm amplifier and filter in this circuit, r l is the tec resistance, r2 is the parasitic resistance of the inductor combined with the equivalent r ds, on of q1 and q2, and r1 is the esr of c1. the voltage, v x , is the pulse-width modulated waveform that switches between pvdd and ground. this is a second-order low-pass filter with an exact cutoff frequency of f rr rrcl c l l = + + () () f cl c = () = r l c l (27) using the recommended values of l1 = 4.7 = ? ? () > z rc 1 1 211 = () ?? out a i r l = () ? out a vd dr lf for f z dd clk clk = () > () C out a vr fl for f z max dd clk clk > () () z 1 but presumably greater than f c , the worst-case output voltage ripple is ? out a v rc f lc f for f z max dd clk clk clk = + () = () () f clk < z 1, can be further simplified to ? out a v lc f for f z max dd clk clk =< () () ? ? ( )
rev. c e16e adn8830 the gate drive outputs for the pwm amplifier at p1 (pin 21) and n1 (pin 22) have a typical nonoverlap delay of 65 ns. this is done to ensure that one fet is completely off before the other fet is turned on, preventing current from shooting through both simultaneously. the input capacitance (c iss ) of the fet should not exceed 5 nf. the p1 and n1 outputs from the adn8830 have a typi cal output impedance of 6 ? ? C C C pri fet lin ds on tec ,, = () r ds, on for the nmos or the pmos depending on the direction of the current flow. in the typical application setup in figure 2, if the tec is cooling the target object, the pmos is sourcing the current. if the tec is heating the object, the nmos will be sinking current. table iv. partial list of capacitors and key specifications value ( f) esr (m )v oltage rating (v) part number manufacturer website 10 60 6.3 nsp100m6.3d2tr nic components www.niccomp.com 22 * 35 8 esrd220m08b cornell dubilier www.cornell-dubilier.com 22 35 8 nsp220m8d5tr nic components www.niccomp.com 22 35 8 eeffd0k220r panasonic www.maco.panasonic.co.jp 47 25 6.3 nsp470m6.3d2tr nic components www.niccomp.com 68 18 8 esrd680m08b cornell dubilier www.cornell-dubilier.com 100 95 10 594d107x_010c2t vishay www.vishay.com * recommend capacitor in typical application circuit figure 1.
rev. c adn8830 e17e although the fets that drive out a alternate between q1 and q2 being on, they have an equivalent series resistance that is equal to a weighted average of their r ds, on values. rdr dr eqiv ds p ds n = + () C pri fet pwm eqiv tec , = () ( p gcl ) is pcvf gcl iss dd clk = () ( c iss ) for the nmos and pmos. both transistors are switching, so p gcl should be calculated for each one and will be added to find the total power dissipated from the circuit. the series resistance of the inductor, r 2 from figure 14, will also exhibit a power dissipation equal to pri r tec 2 2 2 = () p rls at 1 mhz switching frequen- cies and 50% of p rl at 100 khz. judging conservatively pp loss rl = () pvma adn dd 8830 10 = () efficiency is then found by comparing the power dissipated with the required output power to the load. efficiency p pp load load diss tot = + () piv load load load = () () () ( ? ) () ( ) ( ? ) ()
rev. c e18e adn8830 the voltmeter to the tec or output load should include the series ammeter since the power delivered to the ammeter is considered part of the total output power. however, the voltmeter measuring the voltage delivered to the adn8830 circuit should not include the series ammeter from the power supply. this prevents a false supply voltage power measurement since we are interested only in the supply voltage power delivered to the adn8830 circuit. figures 16 and 17 show some efficiency measurements using the typical appli- cation circuit shown in figure 1. i tec (ma) 100 80 0 0 2,000 500 efficiency (%) 1,000 1,500 60 40 20 v sy = 5v v sy = 3v figure 16. efficiency with f clk = 1 mhz i tec (ma) 100 80 0 0 2,000 500 efficiency (%) 1,000 1,500 60 40 20 v sy = 5v v sy = 3v figure 17. efficiency with f clk = 200 khz note that higher efficiency can be achieved using a lower supply voltage or a slower clock frequency. this is due to the fact that the dominant source of power dissipation at high clock frequencies is the gate charge loss on the pwm transistors. layout considerations the two key considerations for laying out the board for the adn8830 are to minimize both the series resistance in the output and the potential noise pickup in the precision input section. the best way to accomplish both of these objectives is to divide the layout into two sections, one for the output components and the other for the remainder of the circuit. these sections should have independent power supply and ground current paths that are each connected together at a single point near the power supply. this is used to minimize power supply and ground voltage bounce on the more sensitive input stages to the adn8830 caused by the switch- ing of the pwm output. such a layout technique is referred to as a
rev. c adn8830 e19e power supply ripple minimizing ripple on the power supply voltage can be an impor- tant consideration, particularly in signal source laser applications. if the laser diode is operated from the same supply rail as the tec controller, ripple on the supply voltage could cause inadvertent modulation of the laser frequency. as most laser diodes are driven from a 5 v supply, it is recommended the adn8830 be operated from a separate 3.3 v regulated supply unless higher tec voltages are required. operation from 3.3 v also improves efficiency, thus minimizing power dissipation. the power supply ripple is primarily a function of the supply by- pass capacitance, also called bulk capacitance, and the inductor ripple current. similar to the l-c filter at the pwm amplifier output, using more capacitance with low equivalent series resis- tance (esr) will lower the supply ripple. a larger inductor value will reduce the inductor ripple current, but this may not be practical in the application. a recommended approach is to use a standard electrolytic capacitor in parallel with a low esr capacitor. a surface-mount 220 ? ? ? ? ? ? ? ( ) ( ) sd on cr cr = = () r s is found as v irr v r out l s dd s = () r l is the load resistance or resistance of the tec and ? ? ? ? ? ( ) ?
rev. c e20e adn8830 if the voltage at v sy drops below v x , q1 is turned off and the vlim pin will be set to 1.5 v, effectively setting the maximum voltage across the outputs to 0 v. the voltage divider for v x is calculated from equation 43. design example 5 a maximum output current limit needs to be set at 1.5 a for a tec with a maximum voltage rating of 2.5 v. the adn8830 is powered from 5 v. the tec resistance is estimated at 1.67 ? = ? = ? vhi vref r i vlo vref r i s limit s limit =+ = + C C ( C ? ? ? ? + + ? ? ? ? = ?
rev. c adn8830 e21e using an rtd for temperature sensing the adn8830 can be used with a resistive temperature device (rtd) as the temperature feedback sensor. the resistance of an rtd is linear with respect to temperature, offering an advan- tage over thermistors that have an exponential relationship to temperature. a constant current applied through an rtd will yield a voltage proportional to temperature. however, this volt- age could be on the order of only 0.5 mv/ C C ? ? ?
rev. c e22e adn8830 outline dimensions 32-lead lead frame chip scale package [lfcsp] (cp-32-1) dimensions shown in millimeters compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 bottom view 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq sq 3.25 3.10 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min
rev. c adn8830 ?3 revision history location page 11/03?ata sheet changed from rev. b to rev. c. changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 deleted figure 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 deleted boosting the output voltage section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 deleted figure 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 deleted equations 45, 46 and 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8/03?ata sheet changed from rev. a to rev. b. updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated thermistor setup section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/03?ata sheet changed from rev. 0 to rev. a. renumbered figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal change to thermistor setup section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 change to figure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 change to figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 change to figure 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 update outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
c02793e0e11/03(c) e24e

▲Up To Search▲

Price & Availability of FDW2520C

	To Download FDW2520C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .